Embodiments relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a storage node contact plug and a method for manufacturing the same.
With the increasing integration of semiconductor devices, the semiconductor device is gradually reduced in size. Thus, the width of a capacitor serving as a memory space for storing data in a memory device such as a Dynamic Random Access Memory (DRAM) is also reduced. In a DRAM, the capacitor is configured by a dielectric film interposed between a storage node and a plate node. Storage capacity (i.e., capacitance) of the above-mentioned capacitor is proportional to a surface area of the node and a dielectric constant (permittivity) of a dielectric film, and is inversely proportional to spacing between nodes or electrodes (i.e., thickness of the dielectric film).
Therefore, in order to implement a high-capacitance capacitor, a dielectric film having high permittivity may be used, a node (electrode) surface area may be increased, and/or the distance between nodes may be reduced.
It may be difficult, however, to reduce the distance between nodes (i.e., thickness of the dielectric film). Accordingly, research for forming a high-capacitance capacitor have been intensively discussed in various ways, for example, a method for using the high-permittivity dielectric film, and a method for increasing the node surface area. A representative method for increasing the node surface area may be implemented as a method for forming a cylindrical three-dimensional (3D) structure. The higher the height of the cylindrical storage node, the larger the node surface area.
A semiconductor device including the cylindrical storage node and a method for manufacturing the same will hereinafter be described with reference to FIG. 1. Referring to FIG. 1, a first interlayer insulation film 15 is formed over the semiconductor substrate 10, which includes an active region and a device isolation film 14. The first interlayer insulation film 15 is etched so that a landing plug contact hole exposing the active region is formed. Thereafter, a conductive material is buried in the landing plug contact hole so that a landing plug contact 16 is formed. Then, a second interlayer insulation film 18 and a first etch stop film 23 are formed over the landing plug contact 16 and the first interlayer insulation film 15. Subsequently, the first etch stop film 23 and the second interlayer insulation film 18 are etched so that a first contact hole exposing the landing plug contact 16 is formed and a first plug 20 is formed by burying the first contact hole.
After a third interlayer insulation film 25 and a second etch stop film 30 are formed over the first plug 20 and the first etch stop film 23, the second etch stop film 30 and the third interlayer insulation film 25 are etched so that a second contact hole exposing the first plug 20 is formed. Thereafter, a conductive material is buried in the second contact hole so that a second plug 35 is formed. In this case, the first plug 20 and the second plug 35 are used as a storage node contact 38.
Thereafter, a first sacrificial film and a second sacrificial film are formed over the storage node contact 38 and the second etch stop film 30. In this case, the first sacrificial film is a Phosphorus Silicate Glass (PSG) film, and the second sacrificial film is a Plasma Enhanced Tetra Ethyle Ortho Silicate (PE-TEOS). Subsequently, the storage node contact 38 is exposed by etching the second sacrificial film and the first sacrificial film, and a first sacrificial film pattern 45a and a second sacrificial film pattern 50a for defining the storage node region 55 are formed. In this case, the PSG film serving as the first sacrificial film is rapidly etched so that a bowing profile occurs in a sidewall of a storage node region 55. Provided that a lower electrode 63 coupled to the storage node contact 38 is formed in the storage node region 55 including the bowing profile, a spatial margin between the lower electrodes 63 becomes insufficient due to the bowing profile, so that a bridge fail occurs, resulting in deterioration of semiconductor device characteristics.